MC9S12E128CFUE

Consult the ATD_10B16C Block Guide for further information about the A/D Converter module. Note that V04 of the ATD has an external trigger (ETRIG) function which is tied off and not available for use. Section 8 Clock Reset Generator (CRG) Block Description Consult the CRG Block Guide for information about the Clock and Reset Generator module.8.1 Device-specific information The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the VREG Block Guide for voltage level specifications. 3F.8.1.1 XCLKS The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7). Section 9 Digital to Analog Converter (DAC) Block Description There are two digital to analog converter modules (DAC0, DAC1). Consult the DAC Block Guide for information about the DAC Module.